Spitzer Documentation & Tools
MIPS Instrument Handbook

 

2.4  Electronics

2.4.1        Hardware

To reduce the cost and mass of the Spitzer spacecraft, much of the electronics required by IRS and MIPS are shared, including a warm electronics chassis, power supplies, the instrument processor (RAD6000) and the control and science data interfaces to the spacecraft computer.  The IRS instrument has four Si focal plane arrays (FPAs) and MIPS relies on the IRS electronics to control and read out the MIPS Si:As FPA.  The block diagram of the combined electronics shown in Figure 2.14 identifies the MIPS electronics, the IRS electronics, and the Common Electronics.

 

The MIPS/IRS warm electronics are designed to be standby-redundant: two identical electronics boxes are flown.  Both boxes are connected to the FPAs and scan mirror in the cold instrument, but only one box is powered at a time.  Each circuit that is connected to the cold instrument is designed so that when the circuit is not powered, it does not load the signal line running from the powered electronics box to the cold instrument.  To provide further protection from failures, each Ge:Ga FPA is treated as two independent arrays.  Independent clock and DC voltages are provided for each 16x32 half of the 70 µm FPA as well as each 2x10 half of the 160 µm FPA. A total of 40 identical analog chains are provided in the MIPS warm electronics for the two Ge:Ga FPAs: 32 for the 70 µm FPA and 8 for the 160 µm one. 

 

The cables connecting the FPA outputs to the MIPS warm electronics are over three meters long.  Since these cables are routed from the 1.5 K instrument out to the 300 K warm electronics box, low thermal conductivity wire is used for these cables.  Each cable contains 24 pairs of twisted pair manganin wire protected by an outer shield; each output signal is twisted with a complementary ground reference.  The total capacitance of the cable, up to 700 pF, must be driven by the array output amplifiers.  An instrumentation amplifier in the warm electronics, which helps reject common mode noise on the incoming signal and ground reference lines, receives the signals.  The output of the instrumentation amplifier is summed with a DC offset voltage and then fed into a 1 KHz two pole filter.  The bandwidth of this filter was chosen to be low enough to limit the FPA noise bandwidth and yet provide a reasonable readout time for the FPA.  The outputs of the 40 analog chains are multiplexed down to a single analog line, which is fed to the analog to digital converter (ADC) as shown in Figure 2.14.  A 16-bit ADC is used to digitize the processed pixel data from the germanium FPAs, with a resolution of 7 electrons per ADU. For that array, the gain is 5 electrons per ADU, again into a 16-bit converter.

 

Figure 2.14: Electronic schematic for MIPS/IRS combined electronics package.

 

As shown in Figure 2.14, a hardware timing generator is used to produce the clock signals for the two MIPS Ge:Ga FPAs, synchronization signals for the MIPS Si:As FPA, and deflection waveforms for the scan mirror.  Synchronizing signals are fed from the MIPS timing generator to the IRS timing pattern generator, which produces the actual Si:As FPA clocking patterns.  Both of these timing generators are implemented in hardware with no real time intrusions required by the instrument processor.  The MIPS flight software controls the operation of these timing generators through register writes.  In operation, the MIPS germanium FPAs are read out at a frequency of 8 Hz and the silicon FPA at 2Hz.

 

The timing in MIPS has been adjusted to be synchronous with the computer oscillator and other potential sources of synchronous noise.  Hence a MIPS second is 5% longer than a conventional one.  In this and other sections of this document time information regarding instrument operations (in particular, read intervals and integration times) is given in 'MIPS time' if not otherwise noted.  In practical terms, the 5% difference is not a concern for observers as it results in slightly longer integration times (and higher sensitivity) than would nominally be achieved.  See section 3.4.1 for specific information regarding the impact on sensitivity and integration time estimates.  Times returned by the archive are in real seconds, and transparently account for the 5% timing stretch within the MIPS hardware.

 

Drivers are provided in the MIPS electronics for the FPA calibration stimulator sources and the thermal anneal heaters.  The timing generator produces the stimulator flash pulses, which are synchronized with the FPA readout.  The thermal anneal heater timing is controlled directly by the instrument processor.  The CSMM (scan mirror) is controlled by a type I analog servo system.  The actual CSMM deflection angle is continuously monitored and compared with the commanded angle.  The error signal between the actual and desired positions is integrated and used to drive the CSMM actuator.  Mirror deflection commands are generated digitally by the timing generator and converted to an analog command using a digital-to-analog converter (DAC).  The timing generator produces all the required CSMM deflection waveforms, including chop waveforms and the sawtooth pattern required by the MIPS scan map mode.  The higher currents required by the CSMM and by the FPA thermal anneal heaters are carried to the cold instrument over a cable constructed of phosphor bronze wire.